A conventional data bus system, such as AMBA (high performance micro-controller bus system) provided by ARM Ltd., which includes a high performance AHB bus and a peripheral APB bus. In this system, a high performance device (bus master) is coupled to the high performance AHB bus. Another bus master, such as a CPU, is also coupled to the high performance AHB bus. An AHB bus arbiter allows selectively one of those two bus masters to access the high performance AHB bus.
According to the above described conventional system, however, the CPU cannot perform any operation while the other bus master, high performance device, is accessing the high performance AHB bus. Even if an interrupt is requested to the CPU, the interrupt operation cannot be carried out until the high performance device stops sending bus request signals. If the system is designed so as that bus requests are provided with a predetermined interval, the performance of the system gets lowered.